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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-20873-4E
FLASH MEMORY
CMOS
32M (4M x 8/2M x 16) BIT
Dual Operation
MBM29DL32XTD/BD
s FEATURES
-80/90/12
* 0.33 m Process Technology * Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes (Refer to Table 1) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program * Single 3.0 V read, program, and erase Minimizes system level power requirements
(Continued)
s PRODUCT LINE UP
Part No. VCC = 3.3 V Ordering Part No. VCC = 3.0 V Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns)
+0.3 V -0.3 V +0.6 V -0.3 V
MBM29DL32XTD/MBM29DL32XBD 80 -- 80 80 30 -- 90 90 90 35 -- 12 120 120 50
s PACKAGES
48-pin plastic TSOP (I)
Marking Side
48-pin plastic TSOP (I)
57-ball plastic FBGA
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(BGA-57P-M01)
Em\edded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
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MBM29DL32XTD/BD-80/90/12
(Continued) * Compatible with JEDEC-standard commands Uses same software commands as E2PROMs * Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: PFTN - Normal Bend Type, PFTR - Reversed Bend Type) 57-ball FBGA (Package suffix: PBT) * Minimum 100,000 program/erase cycles * High performance 80 ns maximum access time * Sector erase architecture Eight 4K word and sixty-three 32K word sectors in word mode Eight 8K byte and sixty-three 64K byte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture T = Top sector B = Bottom sector * Hidden ROM (Hi-ROM) region 64K byte of Hi-ROM, accessible through a new "Hi-ROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC input pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status At VIH, allows removal of boot sector protection At VACC, increases program performance * Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. * Low VCC write inhibit 2.5 V * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device * Sector group protection Hardware method disables any combination of sector groups from program or erase operations * Sector Group Protection Set function by Extended sector group protection command * Fast Programming Function by Extended Command * Temporary sector group unprotection Temporary sector group unprotection via the RESET pin. * In accordance with CFI (Common Flash Memory Interface)
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MBM29DL32XTD/BD-80/90/12
s GENERAL DESCRIPTION
The MBM29DL32XTD/BD are a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes of 8 bits each or 2M words of 16 bits each. The MBM29DL32XTD/BD are offered in a 48-pin TSOP(I) and FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. MBM29DL32XTD/BD are organized into two banks, Bank 1 and Bank 2, which can be considered to be two separate memory arrays as far as certain operations are concerned. These devices are the same as Fujitsu's standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. In the MBM29DL32XTD/BD, a new design concept is implemented, so called "Sliding Bank Architecture". Under this concept, the MBM29DL32XTD/BD can be produced a series of devices with different Bank 1/Bank 2 size combinations; 0.5 Mb/31.5 Mb, 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb. The standard MBM29DL32XTD/BD offer access times 80 ns, 90 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29DL32XTD/BD are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29DL32XTD/BD are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin. A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29DL32XTD/BD are erased when shipped from the factory. The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29DL32XTD/BD memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.
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MBM29DL32XTD/BD-80/90/12
Table 1 Device Part Number MBM29DL321TD/BD MBM29DL322TD/BD MBM29DL323TD/BD MBM29DL324TD/BD x 8/x 16 Organization
MBM29DL32XTD/BD Device Bank Divisions Bank 1 Megabits 0.5 Mbit 4 Mbit 8 Mbit 16 Mbit Sector sizes Eight 8K byte/4K word Eight 8K byte/4K word, seven 64K byte/32K word Eight 8K byte/4K word, fifteen 64K byte/32K word Eight 8K byte/4K word, thirty-one 64K byte/ 32K word Megabits 31.5 Mbit 28 Mbit 24 Mbit 16 Mbit Bank 2 Sector sizes Sixty-three 64K byte/32K word Fifty-six 64K byte/32K word Forty-eight 64K byte/32K word Thirty-two 64K byte/32K word
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MBM29DL32XTD/BD-80/90/12
s PIN ASSIGNMENTS
TSOP(I) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET N.C. WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ 15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0
Standard Pinout
FPT-48P-M19 A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY WP/ACC N.C. RESET WE A20 A19 A8 A9 A10 A11 A12 A13 A14 A15 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16
Reverse Pinout
FPT-48P-M20
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MBM29DL32XTD/BD-80/90/12
(Continued)
FBGA (TOP VIEW) Marking side A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6
(BGA-57P-M01)
A1 B1 C1 D1 E1 F1 G1 H1
A3 A4 A2 A1 A0 CE OE VSS
A2 B2 C2 D2 E2 F2 G2 H2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
A3 B3 C3 D3 E3 F3 G3 H3
RY/BY A18 A20 DQ2 DQ10 DQ11 DQ3
A4 C4 D4 E4 F4 G4 H4
WE RESET N.C. A19 DQ5 DQ12 VCC DQ4
A5 B5 C5 D5 E5 F5 G5 H5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
A6 B6 C6 D6 E6 F6 G6 H6
A13 A12 A14 A15 A16 BYTE DQ15/A-1 VSS
WP/ACC B4
Regarding additional No Internal Connection balls, please contact a Fujitsu representative for more information.
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MBM29DL32XTD/BD-80/90/12
s BLOCK DIAGRAM
V CC V SS
Bank 2 Address A0 to A20 (A-1)
Cell Matrix (Bank 2)
X-Decoder RY/BY State Control & Command Register Status Control DQ 0 to DQ 15
RESET WE CE OE BYTE WP/ACC DQ 0 to DQ 15
X-Decoder Y-Gating & Data Latch
Bank 1 Address
Cell Matrix (Bank 1)
Y-Gating & Data Latch
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MBM29DL32XTD/BD-80/90/12
s LOGIC SYMBOL
Table 2 MBM29DL32XTD/BD Pin Configuration Pin
A-1 21 A0 to A20 DQ 0 to DQ 15 CE OE WE RESET BYTE WP/ACC RY/BY 16 or 8
Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Temporary Sector Group Unprotection Selects 8-bit or 16-bit mode Hardware Write Protection/Program Acceleration No Internal Connection Device Ground Device Power Supply
A-1, A0 to A20 DQ0 to DQ15 CE OE WE RY/BY RESET BYTE WP/ACC N.C. VSS VCC
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MBM29DL32XTD/BD-80/90/12
s DEVICE BUS OPERATION
Table 3 MBM29DL32XTD/BD User Bus Operations (BYTE = VIH) Operation Auto-Select Manufacturer Code (1) Auto-Select Device Code (1) Read (3) Standby Output Disable Write (Program/Erase) Enable Sector Group Protection (2), (4) Verify Sector Group Protection (2), (4) Temporary Sector Group Unprotection (5) Reset (Hardware)/Standby Boot Block Sector Write Protection CE OE WE L L L H L L L L X X X L L L X H H VID L X X X H X X X H H H X H L A0 L H A0 X X A0 L L X X X A1 L L A1 X X A1 H H X X X A6 L L A6 X X A6 L L X X X A9 VID VID A9 X X A9 VID VID X X X DQ0 to DQ15 RESET WP/ACC Code Code DOUT HIGH-Z HIGH-Z DIN X Code X HIGH-Z X H H H H H H H H VID L X X X X X X X X X X X L
Table 4 MBM29DL32XTD/BD User Bus Operations (BYTE = VIL) Operation Auto-Select Manufacturer Code (1) Auto-Select Device code (1) Read (3) Standby Output Disable Write (Program/Erase) Enable Sector Group Protection (2), (4) Verify Sector Group Protection (2), (4) Temporary Sector Group Unprotection (5) Reset (Hardware)/Standby Boot Block Sector Write Protection CE OE WE DQ15/ A0 A-1 L L L H L L L L X X X L L L X H H VID L X X X H X X X H H H X H L L L A-1 X X A-1 L L X X X L H A0 X X A0 L L X X X A1 L L A1 X X A1 H H X X X A6 L L A6 X X A6 L L X X X A9 VID VID A9 X X A9 VID VID X X X DQ0 to DQ7 RESET WP/ACC Code Code DOUT HIGH-Z HIGH-Z DIN X Code X HIGH-Z X H H H H H H H H VID L X X X X X X X X X X X L
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See Table 12. 2. Refer to the section on Sector Group Protection. 3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 4. VCC = 3.3 V 10% 5. It is also used for the extended sector group protection. 9
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MBM29DL32XTD/BD-80/90/12
s ABSOLUTE MAXIMUM RATINGS(See WARNING)
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, RESET (Note 1) Power Supply Voltage (Note 1) A9, OE, and RESET (Note 2) WP/ACC (Note 3) Symbol Tstg TA Conditions Rating Min. -55 -40 Max. +125 +85 Unit C C
VIN, VOUT
-0.5
VCC+0.5
V
VCC VIN VIN
-0.5 -0.5 -0.5
+4.0 +13.0 +10.5
V V V
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Notes: 1. Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitions, inputs may negative overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCC +0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns. 2. Minimum DC input voltage on A9, OE and RESET pins are -0.5 V. During voltage transitions, A9, OE and RESET pins may negative overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of up to 20 ns. when VCC is applied. 3. Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may negative overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin iis +10.5V which may positive overshoot to +10.5V for periods of up to 20ns when Vcc is applied.
s RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature Power Supply Voltage Symbol TA VCC Conditions
MBM29DL32XTD/BD-80 MBM29DL32XTD/BD-90/12 MBM29DL32XTD/BD-80 MBM29DL32XTD/BD-90/12
Value Min. -20 -40 +3.0 +2.7 Max. +70 +85 +3.6 +3.6
Unit C C V V
Operating ranges define those limits between which the functionality of the devices are guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating conditionranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 10
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MBM29DL32XTD/BD-80/90/12
s MAXIMUM OVERSHOOT
+0.6 V -0.5 V -2.0 V
20 ns
20 ns
20 ns
Figure 1 Maximum Negative Overshoot Waveform
20 ns
V CC +2.0 V V CC +0.5 V +2.0 V
20 ns 20 ns
Figure 2 Maximum Positive Overshoot Waveform 1
20 ns
+14.0 V +13.0 V V CC +0.5 V
20 ns 20 ns
*: This waveform is applied for A9, OE, and RESET.
Figure 3 Maximum Positive Overshoot Waveform 2
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MBM29DL32XTD/BD-80/90/12
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter Input Leakage Current Output Leakage Current A9, OE, RESET Inputs Leakage Current Symbol ILI ILO ILIT Conditions VIN = VSS to VCC, VCC = VCC Max. VOUT = VSS to VCC, VCC = VCC Max. VCC = VCC Max. A9, OE, RESET = 12.5 V CE = VIL, OE = VIH, f = 5 MHz VCC Active Current (Note 1) ICC1 CE = VIL, OE = VIH, f = 1 MHz VCC Active Current (Note 2) VCC Current (Standby) VCC Current (Standby, Reset) VCC Current (Automatic Sleep Mode) (Note 3) VCC Active Current (Note 5) (Read-While-Program) VCC Active Current (Note 5) (Read-While-Erase) VCC Active Current (Erase-Suspend-Program) ACC Accelerated Program Current Input Low Level Input High Level Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration Voltage for Autoselect and Sector Protection (A9, OE, RESET) (Note 4) ICC2 ICC3 ICC4 ICC5 CE = VIL, OE = VIH VCC = VCC Max., CE = VCC 0.3 V, RESET = VCC 0.3 V VCC = VCC Max.,WE/ACC = VCC 0.3 V, RESET = VSS 0.3 V VCC = VCC Max., CE = VSS 0.3 V, RESET = VCC 0.3 V VIN = VCC 0.3 V or VSS 0.3 V CE = VIL, OE = VIH CE = VIL, OE = VIH CE = VIL, OE = VIH VCC = VCC Max. WP/ACC = VACC Max. -- -- -- Byte Word Byte Word Byte Word Byte Word Value Min. -1.0 -1.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -0.5 2.0 8.5 Max. +1.0 +1.0 35 16 18 7 7 35 5 5 5 51 53 51 53 35 20 0.6 VCC+0.3 9.5 Unit A A A mA mA mA A A A
ICC6 ICC7 ICC8 IACC VIL VIH VACC
mA mA mA mA V V V
VID
--
11.5
12.5
V
(Continued)
Notes: 1. 2. 3. 4. 5. The ICC current listed includes both the DC operating current and the frequency dependent component. ICC active while Embedded Algorithm (program or erase) is in progress. Automatic sleep mode enables the low power mode when address remain stable for 150 ns. Applicable for only VCC applying. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
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MBM29DL32XTD/BD-80/90/12
(Continued)
Parameter Output Low Voltage Level Output High Voltage Level Low VCC Lock-Out Voltage Notes: 1. 2. 3. 4. 5. Symbol VOL VOH1 VOH2 VLKO Conditions IOL = 4.0 mA, VCC = VCC Min. IOH = -2.0 mA, VCC = VCC Min. IOH = -100 A -- Value Min. -- 2.4 VCC-0.4 2.3 Max. 0.45 -- -- 2.5 Unit V V V V
The ICC current listed includes both the DC operating current and the frequency dependent component. ICC active while Embedded Algorithm (program or erase) is in progress. Automatic sleep mode enables the low power mode when address remain stable for 150 ns. Applicable for only VCC applying. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
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MBM29DL32XTD/BD-80/90/12
2. AC Characteristics
* Read Only Operations Characteristics Parameter symbols JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX -- -- Standard tRC tACC tCE tOE tDF tDF tOH tREADY tELFL tELFH Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time from Addresses, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode CE or BYTE Switching Low or High -- Min. 80 80 80 30 25 25 0 20 5 90 90 90 35 30 30 0 20 5 120 120 120 50 30 30 0 20 5 ns ns ns ns ns ns ns s ns 80 (Note) 90 (Note) 12 (Note)
Description
Test setup
Unit
CE = VIL Max. OE = VIL OE = VIL Max. -- -- -- -- -- -- Max. Max. Max. Min. Max. Max.
Note: Test Conditions: Output Load: 1 TTL gate and 30 pF (MBM29DL32XTD/BD 80) 1 TTL gate and 100 pF (MBM29DL32XTD/BD 90/12) Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output:1.5 V
3.3 V IN3064 or Equivalent Device Under Test 6.2 k CL Diodes = IN3064 or Equivalent
2.7 k
Figure 4 Test Conditions
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MBM29DL32XTD/BD-80/90/12
* Write/Erase/Program Operations Parameter symbols Description JEDEC tAVAV tAVWL -- tWLAX -- tDVWH tWHDX -- -- -- tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 -- -- -- -- -- -- Standard tWC tAS tASO tAH tAHT tDS tDH tOEH tCEPH tOEPH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP tOESP Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CE or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Hold Time Read Toggle and Data Polling Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Typ. Min. Min. Min. Min. Min. Min. 80 0 12 45 0 30 0 0 10 20 20 0 0 0 0 0 0 35 35 25 25 8 1 50 500 500 4 100 4 90 0 15 45 0 35 0 0 10 20 20 0 0 0 0 0 0 35 35 30 30 8 1 50 500 500 4 100 4 120 0 15 50 0 50 0 0 10 20 20 0 0 0 0 0 0 50 50 30 30 8 1 50 500 500 4 100 4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s sec s ns ns s s s 80 90 12 Unit
CE High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write Read Recover Time Before Write CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Byte Programming Operation Sector Erase Operation (Note 1) VCC Setup Time Rise Time to VID (Note 2) Rise Time to VID (Note 2) Voltage Transition Time (Note 2) Write Pulse Width (Note 2) OE Setup Time to WE Active (Note 2)
(Continued)
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MBM29DL32XTD/BD-80/90/12
(Continued)
Parameter symbols Description JEDEC -- -- -- -- -- -- -- -- -- -- Standard tCSP tRB tRP tRH tFLQZ tFHQV tBUSY tEOE tTOW tSPD CE Setup Time to WE Active (Note 2) Recover Time from RY/BY RESET Pulse Width RESET High Level Period before Read BYTE Switching Low to Output High-Z BYTE Switching High to Output Active Program/Erase Valid to RY/BY Delay Min. Min. Min. Min. Max. Max. Max. 4 0 500 200 30 80 90 80 50 20 4 0 500 200 30 90 90 90 50 20 4 0 500 200 40 120 90 120 50 20 s ns ns ns ns ns ns ns s s 80 90 12 Unit
Delay Time from Embedded Output Enable Max. Erase Time-Out Time Erase Suspend Transition Time Min. Max.
Notes: 1. This does not include the preprogramming time. 2. This timing is for Sector Group Protection operation.
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MBM29DL32XTD/BD-80/90/12
s ERASE AND PROGRAMMING PERFORMANCE
Limits Parameter Min. Sector Erase Time Word Programming Time Byte Programming Time Chip Programming Time Program/Erase Cycle -- -- -- -- 100,000 Typ. 1 16 8 -- -- Max. 10 360 300 100 -- sec s s sec cycles Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead -- Unit Comments
s PIN CAPACITANCE
Parameter symbol CIN COUT CIN2 CIN3 Parameter description Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Test setup VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Typ. 6 8.5 8 21.5 Max. 7.5 12 11 22.5 Unit pF pF pF pF
Note: Test conditions TA = 25C, f = 1.0 MHzs
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MBM29DL32XTD/BD-80/90/12
s TIMING DIAGRAM
* Key to Switching Waveforms
WAVEFORM
INPUTS Must Be Steady May Change from H to L May Change from L to H "H" or "L" Any Change Permitted Does Not Apply
OUTPUTS Will Be Steady Will Be Changing from H to L Will Be Changing from L to H Changing State Unknown Center Line is HighImpedance "Off" State
t RC
Addresses
Addresses Stable
t ACC
CE
t OE t DF
OE
t OEH
WE
t CE t OH
Outputs
High-Z
Output Valid
High-Z
Figure 5.1 AC Waveforms for Read Operations
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MBM29DL32XTD/BD-80/90/12
t RC
Addresses
t ACC
Addresses Stable
CE
t RH
t
RP
t
RH
t
CE
RESET
t OH
Outputs
High-Z
Output Valid
Figure 5.2 AC Waveforms for Hardware Reset/Read Operations
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MBM29DL32XTD/BD-80/90/12
3rd Bus Cycle Addresses
555H t WC PA t AS t AH
Data Polling
PA t RC
CE
t CS t CH t CE
OE
t GHWL t WP t WPH t WHWH1 t OE
WE
t DS t DH t OH
Data
A0H
PD
DQ 7
D OUT
D OUT
Notes: 1. 2. 3. 4. 5. 6.
PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. These waveforms are for the x16 mode. (The addresses differ from x8 mode.)
Figure 6 AC Waveforms for Alternate WE Controlled Program Operations
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MBM29DL32XTD/BD-80/90/12
3rd Bus Cycle
Data Polling PA t AS t AH PA
Addresses
555H t WC
WE
t WS t WH
OE
t GHEL t CP t CPH t WHWH1
CE
t DS t DH
Data
A0H
PD
DQ 7
D OUT
Notes: 1. 2. 3. 4. 5. 6.
PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. These waveforms are for the x16 mode. (The addresses differ from x8 mode.)
Figure 7 AC Waveforms for Alternate CE Controlled Program Operations
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MBM29DL32XTD/BD-80/90/12
Addresses
555H t WC
2AAH t AS t AH
555H
555H
2AAH
SA *
CE
t CS t CH
OE
t GHWL t WP t WPH
WE
t DS AAH
t DH 55H 80H AAH 55H 10H/ 30H
Data
t VCS
V CC
*: SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte) for Chip Erase. Note: These waveforms are for the x16 mode. (The addresses differ from x8 mode.)
Figure 8 AC Waveforms for Chip/Sector Erase Operations
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MBM29DL32XTD/BD-80/90/12
CE
t CH
t OE
t DF
OE
t OEH
WE
t CE
*
DQ7
Data DQ7 DQ7 = Valid Data
High-Z
t WHWH1 or 2
DQ0 to DQ6
Data t BUSY
DQ0 to DQ6 = Output Flag t EOE
DQ0 to DQ6 Valid Data
High-Z
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation). Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations
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MBM29DL32XTD/BD-80/90/12
Address
tAHT tASO tAHT tAS
CE
tCEPH
WE
tOEH
tOEPH tOEH
OE
tDH tOE tCE
DQ 6/DQ2
Data
tBUSY
Toggle Data
Toggle Data
Toggle Data
*
Stop
Toggling
Output Valid
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation). Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
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MBM29DL32XTD/BD-80/90/12
Read
tRC
Command
tWC
Read
tRC
Command
tWC
Read
tRC
Read
tRC
Address
BA1
tAS
BA2 (555H)
tAH tACC
BA1
BA2 (PA)
BA1
tAS tAHT
BA2 (PA)
tCE
CE
tOE tCEPH
OE
tGHWL tWP tOEH tDF
WE
tDS tDH tDF
DQ
Valid Output
Valid Intput (A0H)
Valid Output
Valid Intput (PD)
Valid Output
Status
Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Bank 1. BA2: Address of Bank 2. Figure 11 Bank-to-bank Read/Write Timing Diagram
Enter Embedded Erasing WE
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2 Toggle DQ2 and DQ6 with OE or CE
Note: DQ2 is read from the erase-suspended sector.
Figure 12 DQ2 vs. DQ6 25
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MBM29DL32XTD/BD-80/90/12
CE
The rising edge of the last write pulse
WE
Entire programming or erase operations
RY/BY
t BUSY
Figure 13 RY/BY Timing Diagram during Program/Erase Operations
WE
RESET
tRP t RB
RY/BY
tREADY
Figure 14 RESET, RY/BY Timing Diagram
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MBM29DL32XTD/BD-80/90/12
CE
tCE
BYTE
Data Output (DQ0 to DQ7) tELFH tFHQV A-1 DQ15 Data Output (DQ0 to DQ14)
DQ0 to DQ14
DQ15/A-1
Figure 15 Timing Diagram for Word Mode Configuration
CE
BYTE
tELFL
DQ0 to DQ14
Data Output (DQ0 to DQ14) tACC
Data Output (DQ0 to DQ7)
DQ15/A-1
DQ15 tFLQZ
A-1
Figure 16 Timing Diagram for Byte Mode Configuration
The falling edge of the last write signal
CE or WE
BYTE
tSET (tAS)
Input Valid
tHOLD (tAH)
Figure 17 BYTE Timing Diagram for Write Operations 27
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MBM29DL32XTD/BD-80/90/12
A20, A19, A18 A17, A16, A15 A14, A13, A12 A0
SGAX
SGAY
A1
A6
VID 3V A9
t VLHT
VID 3V OE
t VLHT t WPP t VLHT t VLHT
WE
t OESP
CE
t CSP
Data
t VCS t OE
01H
VCC
SGAX : Sector Group Address for initial sector SGAY : Sector Group Address for next sector Note: A-1 is VIL on byte mode. Figure 18 AC Waveforms for Sector Group Protection
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MBM29DL32XTD/BD-80/90/12
VCC tVCS VID 3V RESET
tVIDR tVLHT
3V
CE
WE tVLHT RY/BY Unprotection period Program or Erase Command Sequence tVLHT
Figure 19 Temporary Sector Group Unprotection Timing Diagram
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MBM29DL32XTD/BD-80/90/12
VCC
tVCS
RESET tVIDR Add
tVLHT tWC tWC SGAX SGAX SGAY
A0
A1
A6
CE
OE tWP WE TIME-OUT
Data
60H
60H
40H tOE
01H
60H
SGAX : Sector Group Address to be protected SGAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 s (min) Figure 20 Extended Sector Group Protection Timing Diagram
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MBM29DL32XTD/BD-80/90/12
VCC tVCS VACC 3V WP/ACC
tVACCR tVLHT
3V
CE
WE tVLHT RY/BY Acceleration period Program or Erase Command Sequence tVLHT
Figure 21 Accelerated Program Timing Diagram
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MBM29DL32XTD/BD-80/90/12
s FLEXIBLE SECTOR-ERASE ARCHITECTURE
Table 5.1 Sector Address Tables (MBM29DL321TD) Bank
Sector size Sector Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords)
Sector address
(x8) Address range 00000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 7FFFFH 80000H to 8FFFFH 90000H to 9FFFFH A0000H to AFFFFH B0000H to BFFFFH C0000H to CFFFFH D0000H to DFFFFH E0000H to EFFFFH F0000H to FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1FFFFFH 200000H to 20FFFFH 210000H to 21FFFFH 220000H to 22FFFFH
(x16) Address range 000000H to 007FFFH 008000H to 00FFFFH 010000H to 017FFFH 018000H to 01FFFFH 020000H to 027FFFH 028000H to 02FFFFH 030000H to 037FFFH 038000H to 03FFFFH 040000H to 047FFFH 048000H to 04FFFFH 050000H to 057FFFH 058000H to 05FFFFH 060000H to 067FFFH 068000H to 06FFFFH 070000H to 077FFFH 078000H to 07FFFFH 080000H to 087FFFH 088000H to 08FFFFH 090000H to 097FFFH 098000H to 09FFFFH 0A0000H to 0A7FFFH 0A8000H to 0AFFFFH 0B0000H to 0B7FFFH 0B8000H to 0BFFFFH 0C0000H to 0C7FFFH 0C8000H to 0CFFFFH 0D0000H to 0D7FFFH 0D8000H to 0DFFFFH 0E0000H to 0E7FFFH 0E8000H to 0EFFFFH 0F0000H to 0F7FFFH 0F8000H to 0FFFFFH 100000H to 107FFFH 108000H to 10FFFFH 110000H to 117FFFH
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 Bank 2 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32
(Continued)
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MBM29DL32XTD/BD-80/90/12
(Continued)
Bank Sector SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 Bank 2 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 Bank 1 SA67 SA68 SA69 SA70 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 (x8) Address range 230000H to 23FFFFH 240000H to 24FFFFH 250000H to 25FFFFH 260000H to 26FFFFH 270000H to 27FFFFH 280000H to 28FFFFH 290000H to 29FFFFH 2A0000H to 2AFFFFH 2B0000H to 2BFFFFH 2C0000H to 2CFFFFH 2D0000H to 2DFFFFH 2E0000H to 2EFFFFH 2F0000H to 2FFFFFH 300000H to 30FFFFH 310000H to 31FFFFH 320000H to 32FFFFH 330000H to 33FFFFH 340000H to 34FFFFH 350000H to 35FFFFH 360000H to 36FFFFH 370000H to 37FFFFH 380000H to 38FFFFH 390000H to 39FFFFH 3A0000H to 3AFFFFH 3B0000H to 3BFFFFH 3C0000H to 3CFFFFH 3D0000H to 3DFFFFH 3E0000H to 3EFFFFH 3F0000H to 3F1FFFH 3F2000H to 3F3FFFH 3F4000H to 3F5FFFH 3F6000H to 3F7FFFH 3F8000H to 3F9FFFH 3FA000H to 3FBFFFH 3FC000H to 3FDFFFH 3FE000H to 3FFFFFH (x16) Address range 118000H to 11FFFFH 120000H to 127FFFH 128000H to 12FFFFH 130000H to 137FFFH 138000H to 13FFFFH 140000H to 147FFFH 148000H to 14FFFFH 150000H to 157FFFH 158000H to 15FFFFH 160000H to 167FFFH 168000H to 16FFFFH 170000H to 177FFFH 178000H to 17FFFFH 180000H to 187FFFH 188000H to 18FFFFH 190000H to 197FFFH 198000H to 19FFFFH 1A0000H to 1A7FFFH 1A8000H to 1AFFFFH 1B0000H to 1B7FFFH 1B8000H to 1BFFFFH 1C0000H to 1C7FFFH 1C8000H to 1CFFFFH 1D0000H to 1D7FFFH 1D8000H to 1DFFFFH 1E0000H to 1E7FFFH 1E8000H to 1EFFFFH 1F0000H to 1F7FFFH 1F8000H to 1F8FFFH 1F9000H to 1F9FFFH 1FA000H to 1FAFFFH 1FB000H to 1FBFFFH 1FC000H to 1FCFFFH 1FD000H to 1FDFFFH 1FE000H to 1FEFFFH 1FF000H to 1FFFFFH
MBM29DL321TD Top Boot Sector Architecture Note: The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH).
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MBM29DL32XTD/BD-80/90/12
Table 5.2 Sector Address Tables (MBM29DL321BD) Bank Sector SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 Bank 2 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 SA38 SA37 SA36 SA35 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address range 3F0000H to 3FFFFFH 3E0000H to 3EFFFFH 3D0000H to 3DFFFFH 3C0000H to 3CFFFFH 3B0000H to 3BFFFFH 3A0000H to 3AFFFFH 390000H to 39FFFFH 380000H to 38FFFFH 370000H to 37FFFFH 360000H to 36FFFFH 350000H to 35FFFFH 340000H to 34FFFFH 330000H to 33FFFFH 320000H to 32FFFFH 310000H to 31FFFFH 300000H to 30FFFFH 2F0000H to 2FFFFFH 2E0000H to 2EFFFFH 2D0000H to 2DFFFFH 2C0000H to 2CFFFFH 2B0000H to 2BFFFFH 2A0000H to 2AFFFFH 290000H to 29FFFFH 280000H to 28FFFFH 270000H to 27FFFFH 260000H to 26FFFFH 250000H to 25FFFFH 240000H to 24FFFFH 230000H to 23FFFFH 220000H to 22FFFFH 210000H to 21FFFFH 200000H to 20FFFFH 1F0000H to 1FFFFFH 1E0000H to 1EFFFFH 1D0000H to 1DFFFFH 1C0000H to 1CFFFFH (x16) Address range 1F8000H to 1FFFFFH 1F0000H to 1F7FFFH 1E8000H to 1EFFFFH 1E0000H to 1E7FFFH 1D8000H to 1DFFFFH 1D0000H to 1D7FFFH 1C8000H to 1CFFFFH 1C0000H to 1C7FFFH 1B8000H to 1BFFFFH 1B0000H to 1B7FFFH 1A8000H to 1AFFFFH 1A0000H to 1A7FFFH 198000H to 19FFFFH 190000H to 197FFFH 188000H to 18FFFFH 180000H to 187FFFH 178000H to 17FFFFH 170000H to 177FFFH 168000H to 16FFFFH 160000H to 167FFFH 158000H to 15FFFFH 150000H to 157FFFH 148000H to 14FFFFH 140000H to 147FFFH 138000H to 13FFFFH 130000H to 137FFFH 128000H to 12FFFFH 120000H to 127FFFH 118000H to 11FFFFH 110000H to 117FFFH 108000H to 10FFFFH 100000H to 107FFFH 0F8000H to 0FFFFFH 0F0000H to 0F7FFFH 0E8000H to 0EFFFFH 0E0000H to 0E7FFFH
(Continued)
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MBM29DL32XTD/BD-80/90/12
(Continued)
Bank Sector SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 Bank 2 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 Bank 1 SA3 SA2 SA1 SA0 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 0 0 1 1 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 (x8) Address range 1B0000H to 1BFFFFH 1A0000H to 1AFFFFH 190000H to 19FFFFH 180000H to 18FFFFH 170000H to 17FFFFH 160000H to 16FFFFH 150000H to 15FFFFH 140000H to 14FFFFH 130000H to 13FFFFH 120000H to 12FFFFH 110000H to 11FFFFH 100000H to 10FFFFH 0F0000H to 0FFFFFH 0E0000H to 0EFFFFH 0D0000H to 0DFFFFH 0C0000H to 0CFFFFH 0B0000H to 0BFFFFH 0A0000H to 0AFFFFH 090000H to 09FFFFH 080000H to 08FFFFH 070000H to 07FFFFH 060000H to 06FFFFH 050000H to 05FFFFH 040000H to 04FFFFH 030000H to 03FFFFH 020000H to 02FFFFH 010000H to 01FFFFH 00E000H to 00FFFFH 00C000H to 00DFFFH 00A000H to 00BFFFH 008000H to 009FFFH 006000H to 007FFFH 004000H to 005FFFH 002000H to 003FFFH 000000H to 001FFFH (x16) Address range 0D8000H to 0DFFFFH 0D0000H to 0D7FFFH 0C8000H to 0CFFFFH 0C0000H to 0C7FFFH 0B8000H to 0BFFFFH 0B0000H to 0B7FFFH 0A8000H to 0AFFFFH 0A0000H to 0A7FFFH 098000H to 09FFFFH 090000H to 097FFFH 088000H to 08FFFFH 080000H to 087FFFH 078000H to 07FFFFH 070000H to 077FFFH 068000H to 06FFFFH 060000H to 067FFFH 058000H to 05FFFFH 050000H to 057FFFH 048000H to 04FFFFH 040000H to 047FFFH 038000H to 03FFFFH 030000H to 037FFFH 028000H to 02FFFFH 020000H to 027FFFH 018000H to 01FFFFH 010000H to 017FFFH 008000H to 00FFFFH 007000H to 007FFFH 006000H to 006FFFH 005000H to 005FFFH 004000H to 004FFFH 003000H to 003FFFH 002000H to 002FFFH 001000H to 001FFFH 000000H to 000FFFH
MBM29DL321BD Bottom Boot Sector Architecture Note: The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH).
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MBM29DL32XTD/BD-80/90/12
Table 6.1 Sector Address Tables (MBM29DL322TD) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 Bank 2 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address range 000000H to 00FFFFH 010000H to 01FFFFH 020000H to 02FFFFH 030000H to 03FFFFH 040000H to 04FFFFH 050000H to 05FFFFH 060000H to 06FFFFH 070000H to 07FFFFH 080000H to 08FFFFH 090000H to 09FFFFH 0A0000H to 0AFFFFH 0B0000H to 0BFFFFH 0C0000H to 0CFFFFH 0D0000H to 0DFFFFH 0E0000H to 0EFFFFH 0F0000H to 0FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1FFFFFH 200000H to 20FFFFH 210000H to 21FFFFH 220000H to 22FFFFH (x16) Address range 000000H to 007FFFH 008000H to 00FFFFH 010000H to 017FFFH 018000H to 01FFFFH 020000H to 027FFFH 028000H to 02FFFFH 030000H to 037FFFH 038000H to 03FFFFH 040000H to 047FFFH 048000H to 04FFFFH 050000H to 057FFFH 058000H to 05FFFFH 060000H to 067FFFH 068000H to 06FFFFH 070000H to 077FFFH 078000H to 07FFFFH 080000H to 087FFFH 088000H to 08FFFFH 090000H to 097FFFH 098000H to 09FFFFH 0A0000H to 0A7FFFH 0A8000H to 0AFFFFH 0B0000H to 0B7FFFH 0B8000H to 0BFFFFH 0C0000H to 0C7FFFH 0C8000H to 0CFFFFH 0D0000H to 0D7FFFH 0D8000H to 0DFFFFH 0E0000H to 0E7FFFH 0E8000H to 0EFFFFH 0F0000H to 0F7FFFH 0F8000H to 0FFFFFH 100000H to 107FFFH 108000H to 10FFFFH 110000H to 117FFFH
(Continued)
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MBM29DL32XTD/BD-80/90/12
(Continued)
Bank Sector SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 Bank 2 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 Bank 1 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 (x8) Address range 230000H to 23FFFFH 240000H to 24FFFFH 250000H to 25FFFFH 260000H to 26FFFFH 270000H to 27FFFFH 280000H to 28FFFFH 290000H to 29FFFFH 2A0000H to 2AFFFFH 2B0000H to 2BFFFFH 2C0000H to 2CFFFFH 2D0000H to 2DFFFFH 2E0000H to 2EFFFFH 2F0000H to 2FFFFFH 300000H to 30FFFFH 310000H to 31FFFFH 320000H to 32FFFFH 330000H to 33FFFFH 340000H to 34FFFFH 350000H to 35FFFFH 360000H to 36FFFFH 370000H to 37FFFFH 380000H to 38FFFFH 390000H to 39FFFFH 3A0000H to 3AFFFFH 3B0000H to 3BFFFFH 3C0000H to 3CFFFFH 3D0000H to 3DFFFFH 3E0000H to 3EFFFFH 3F0000H to 3F1FFFH 3F2000H to 3F3FFFH 3F4000H to 3F5FFFH 3F6000H to 3F7FFFH 3F8000H to 3F9FFFH 3FA000H to 3FBFFFH 3FC000H to 3FDFFFH 3FE000H to 3FFFFFH (x16) Address range 118000H to 11FFFFH 120000H to 127FFFH 128000H to 12FFFFH 130000H to 137FFFH 138000H to 13FFFFH 140000H to 147FFFH 148000H to 14FFFFH 150000H to 157FFFH 158000H to 15FFFFH 160000H to 167FFFH 168000H to 16FFFFH 170000H to 177FFFH 178000H to 17FFFFH 180000H to 187FFFH 188000H to 18FFFFH 190000H to 197FFFH 198000H to 19FFFFH 1A0000H to 1A7FFFH 1A8000H to 1AFFFFH 1B0000H to 1B7FFFH 1B8000H to 1BFFFFH 1C0000H to 1C7FFFH 1C8000H to 1CFFFFH 1D0000H to 1D7FFFH 1D8000H to 1DFFFFH 1E0000H to 1E7FFFH 1E8000H to 1EFFFFH 1F0000H to 1F7FFFH 1F8000H to 1F8FFFH 1F9000H to 1F9FFFH 1FA000H to 1FAFFFH 1FB000H to 1FBFFFH 1FC000H to 1FCFFFH 1FD000H to 1FDFFFH 1FE000H to 1FEFFFH 1FF000H to 1FFFFFH
MBM29DL322TD Top Boot Sector Architecture Note: The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH).
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Table 6.2 Sector Address Tables (MBM29DL322BD) Bank Sector SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 Bank 2 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 SA38 SA37 SA36 SA35 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address range 3F0000H to 3FFFFFH 3E0000H to 3EFFFFH 3D0000H to 3DFFFFH 3C0000H to 3CFFFFH 3B0000H to 3BFFFFH 3A0000H to 3AFFFFH 390000H to 39FFFFH 380000H to 38FFFFH 370000H to 37FFFFH 360000H to 36FFFFH 350000H to 35FFFFH 340000H to 34FFFFH 330000H to 33FFFFH 320000H to 32FFFFH 310000H to 31FFFFH 300000H to 30FFFFH 2F0000H to 2FFFFFH 2E0000H to 2EFFFFH 2D0000H to 2DFFFFH 2C0000H to 2CFFFFH 2B0000H to 2BFFFFH 2A0000H to 2AFFFFH 290000H to 29FFFFH 280000H to 28FFFFH 270000H to 27FFFFH 260000H to 26FFFFH 250000H to 25FFFFH 240000H to 24FFFFH 230000H to 23FFFFH 220000H to 22FFFFH 210000H to 21FFFFH 200000H to 20FFFFH 1F0000H to 1FFFFFH 1E0000H to 1EFFFFH 1D0000H to 1DFFFFH 1C0000H to 1CFFFFH (x16) Address range 1F8000H to 1FFFFFH 1F0000H to 1F7FFFH 1E8000H to 1EFFFFH 1E0000H to 1E7FFFH 1D8000H to 1DFFFFH 1D0000H to 1D7FFFH 1C8000H to 1CFFFFH 1C0000H to 1C7FFFH 1B8000H to 1BFFFFH 1B0000H to 1B7FFFH 1A8000H to 1AFFFFH 1A0000H to 1A7FFFH 198000H to 19FFFFH 190000H to 197FFFH 188000H to 18FFFFH 180000H to 187FFFH 178000H to 17FFFFH 170000H to 177FFFH 168000H to 16FFFFH 160000H to 167FFFH 158000H to 15FFFFH 150000H to 157FFFH 148000H to 14FFFFH 140000H to 147FFFH 138000H to 13FFFFH 130000H to 137FFFH 128000H to 12FFFFH 120000H to 127FFFH 118000H to 11FFFFH 110000H to 117FFFH 108000H to 10FFFFH 100000H to 107FFFH 0F8000H to 0FFFFFH 0F0000H to 0F7FFFH 0E8000H to 0EFFFFH 0E0000H to 0E7FFFH
(Continued)
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MBM29DL32XTD/BD-80/90/12
(Continued)
Bank Sector SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 Bank 2 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 Bank 1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 0 0 1 1 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 (x8) Address range 1B0000H to 1BFFFFH 1A0000H to 1AFFFFH 190000H to 19FFFFH 180000H to 18FFFFH 170000H to 17FFFFH 160000H to 16FFFFH 150000H to 15FFFFH 140000H to 14FFFFH 130000H to 13FFFFH 120000H to 12FFFFH 110000H to 11FFFFH 100000H to 10FFFFH 0F0000H to 0FFFFFH 0E0000H to 0EFFFFH 0D0000H to 0DFFFFH 0C0000H to 0CFFFFH 0B0000H to 0BFFFFH 0A0000H to 0AFFFFH 090000H to 09FFFFH 080000H to 08FFFFH 070000H to 07FFFFH 060000H to 06FFFFH 050000H to 05FFFFH 040000H to 04FFFFH 030000H to 03FFFFH 020000H to 02FFFFH 010000H to 01FFFFH 00E000H to 00FFFFH 00C000H to 00DFFFH 00A000H to 00BFFFH 008000H to 009FFFH 006000H to 007FFFH 004000H to 005FFFH 002000H to 003FFFH 000000H to 001FFFH (x16) Address range 0D8000H to 0DFFFFH 0D0000H to 0D7FFFH 0C8000H to 0CFFFFH 0C0000H to 0C7FFFH 0B8000H to 0BFFFFH 0B0000H to 0B7FFFH 0A8000H to 0AFFFFH 0A0000H to 0A7FFFH 098000H to 09FFFFH 090000H to 097FFFH 088000H to 08FFFFH 080000H to 087FFFH 078000H to 07FFFFH 070000H to 077FFFH 068000H to 06FFFFH 060000H to 067FFFH 058000H to 05FFFFH 050000H to 057FFFH 048000H to 04FFFFH 040000H to 047FFFH 038000H to 03FFFFH 030000H to 037FFFH 028000H to 02FFFFH 020000H to 027FFFH 018000H to 01FFFFH 010000H to 017FFFH 008000H to 00FFFFH 007000H to 007FFFH 006000H to 006FFFH 005000H to 005FFFH 004000H to 004FFFH 003000H to 003FFFH 002000H to 002FFFH 001000H to 001FFFH 000000H to 000FFFH
MBM29DL322BD Bottom Boot Sector Architecture Note: The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH).
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MBM29DL32XTD/BD-80/90/12
Table 7.1 Sector Address Tables (MBM29DL323TD) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 Bank 2 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address range 000000H to 00FFFFH 010000H to 01FFFFH 020000H to 02FFFFH 030000H to 03FFFFH 040000H to 04FFFFH 050000H to 05FFFFH 060000H to 06FFFFH 070000H to 07FFFFH 080000H to 08FFFFH 090000H to 09FFFFH 0A0000H to 0AFFFFH 0B0000H to 0BFFFFH 0C0000H to 0CFFFFH 0D0000H to 0DFFFFH 0E0000H to 0EFFFFH 0F0000H to 0FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1FFFFFH 200000H to 20FFFFH 210000H to 21FFFFH 220000H to 22FFFFH (x16) Address range 000000H to 007FFFH 008000H to 00FFFFH 010000H to 017FFFH 018000H to 01FFFFH 020000H to 027FFFH 028000H to 02FFFFH 030000H to 037FFFH 038000H to 03FFFFH 040000H to 047FFFH 048000H to 04FFFFH 050000H to 057FFFH 058000H to 05FFFFH 060000H to 067FFFH 068000H to 06FFFFH 070000H to 077FFFH 078000H to 07FFFFH 080000H to 087FFFH 088000H to 08FFFFH 090000H to 097FFFH 098000H to 09FFFFH 0A0000H to 0A7FFFH 0A8000H to 0AFFFFH 0B0000H to 0B7FFFH 0B8000H to 0BFFFFH 0C0000H to 0C7FFFH 0C8000H to 0CFFFFH 0D0000H to 0D7FFFH 0D8000H to 0DFFFFH 0E0000H to 0E7FFFH 0E8000H to 0EFFFFH 0F0000H to 0F7FFFH 0F8000H to 0FFFFFH 100000H to 107FFFH 108000H to 10FFFFH 110000H to 117FFFH
(Continued)
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MBM29DL32XTD/BD-80/90/12
(Continued)
Bank Sector SA35 SA36 SA37 SA38 SA39 SA40 Bank 2 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 Bank 1 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 (x8) Address range 230000H to 23FFFFH 240000H to 24FFFFH 250000H to 25FFFFH 260000H to 26FFFFH 270000H to 27FFFFH 280000H to 28FFFFH 290000H to 29FFFFH 2A0000H to 2AFFFFH 2B0000H to 2BFFFFH 2C0000H to 2CFFFFH 2D0000H to 2DFFFFH 2E0000H to 2EFFFFH 2F0000H to 2FFFFFH 300000H to 30FFFFH 310000H to 31FFFFH 320000H to 32FFFFH 330000H to 33FFFFH 340000H to 34FFFFH 350000H to 35FFFFH 360000H to 36FFFFH 370000H to 37FFFFH 380000H to 38FFFFH 390000H to 39FFFFH 3A0000H to 3AFFFFH 3B0000H to 3BFFFFH 3C0000H to 3CFFFFH 3D0000H to 3DFFFFH 3E0000H to 3EFFFFH 3F0000H to 3F1FFFH 3F2000H to 3F3FFFH 3F4000H to 3F5FFFH 3F6000H to 3F7FFFH 3F8000H to 3F9FFFH 3FA000H to 3FBFFFH 3FC000H to 3FDFFFH 3FE000H to 3FFFFFH (x16) Address range 118000H to 11FFFFH 120000H to 127FFFH 128000H to 12FFFFH 130000H to 137FFFH 138000H to 13FFFFH 140000H to 147FFFH 148000H to 14FFFFH 150000H to 157FFFH 158000H to 15FFFFH 160000H to 167FFFH 168000H to 16FFFFH 170000H to 177FFFH 178000H to 17FFFFH 180000H to 187FFFH 188000H to 18FFFFH 190000H to 197FFFH 198000H to 19FFFFH 1A0000H to 1A7FFFH 1A8000H to 1AFFFFH 1B0000H to 1B7FFFH 1B8000H to 1BFFFFH 1C0000H to 1C7FFFH 1C8000H to 1CFFFFH 1D0000H to 1D7FFFH 1D8000H to 1DFFFFH 1E0000H to 1E7FFFH 1E8000H to 1EFFFFH 1F0000H to 1F7FFFH 1F8000H to 1F8FFFH 1F9000H to 1F9FFFH 1FA000H to 1FAFFFH 1FB000H to 1FBFFFH 1FC000H to 1FCFFFH 1FD000H to 1FDFFFH 1FE000H to 1FEFFFH 1FF000H to 1FFFFFH
MBM29DL323TD Top Boot Sector Architecture
Note: The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH).
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MBM29DL32XTD/BD-80/90/12
Table 7.2 Sector Address Tables (MBM29DL323BD) Bank Sector SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 Bank 2 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 SA38 SA37 SA36 SA35 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address range 3F0000H to 3FFFFFH 3E0000H to 3EFFFFH 3D0000H to 3DFFFFH 3C0000H to 3CFFFFH 3B0000H to 3BFFFFH 3A0000H to 3AFFFFH 390000H to 39FFFFH 380000H to 38FFFFH 370000H to 37FFFFH 360000H to 36FFFFH 350000H to 35FFFFH 340000H to 34FFFFH 330000H to 33FFFFH 320000H to 32FFFFH 310000H to 31FFFFH 300000H to 30FFFFH 2F0000H to 2FFFFFH 2E0000H to 2EFFFFH 2D0000H to 2DFFFFH 2C0000H to 2CFFFFH 2B0000H to 2BFFFFH 2A0000H to 2AFFFFH 290000H to 29FFFFH 280000H to 28FFFFH 270000H to 27FFFFH 260000H to 26FFFFH 250000H to 25FFFFH 240000H to 24FFFFH 230000H to 23FFFFH 220000H to 22FFFFH 210000H to 21FFFFH 200000H to 20FFFFH 1F0000H to 1FFFFFH 1E0000H to 1EFFFFH 1D0000H to 1DFFFFH 1C0000H to 1CFFFFH (x16) Address range 1F8000H to 1FFFFFH 1F0000H to 1F7FFFH 1E8000H to 1EFFFFH 1E0000H to 1E7FFFH 1D8000H to 1DFFFFH 1D0000H to 1D7FFFH 1C8000H to 1CFFFFH 1C0000H to 1C7FFFH 1B8000H to 1BFFFFH 1B0000H to 1B7FFFH 1A8000H to 1AFFFFH 1A0000H to 1A7FFFH 198000H to 19FFFFH 190000H to 197FFFH 188000H to 18FFFFH 180000H to 187FFFH 178000H to 17FFFFH 170000H to 177FFFH 168000H to 16FFFFH 160000H to 167FFFH 158000H to 15FFFFH 150000H to 157FFFH 148000H to 14FFFFH 140000H to 147FFFH 138000H to 13FFFFH 130000H to 137FFFH 128000H to 12FFFFH 120000H to 127FFFH 118000H to 11FFFFH 110000H to 117FFFH 108000H to 10FFFFH 100000H to 107FFFH 0F8000H to 0FFFFFH 0F0000H to 0F7FFFH 0E8000H to 0EFFFFH 0E0000H to 0E7FFFH
(Continued)
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MBM29DL32XTD/BD-80/90/12
(Continued)
Bank Sector SA34 SA33 SA32 SA31 SA30 SA29 Bank 2 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 Bank 1 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 0 0 1 1 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 (x8) Address range 1B0000H to 1BFFFFH 1A0000H to 1AFFFFH 190000H to 19FFFFH 180000H to 18FFFFH 170000H to 17FFFFH 160000H to 16FFFFH 150000H to 15FFFFH 140000H to 14FFFFH 130000H to 13FFFFH 120000H to 12FFFFH 110000H to 11FFFFH 100000H to 10FFFFH 0F0000H to 0FFFFFH 0E0000H to 0EFFFFH 0D0000H to 0DFFFFH 0C0000H to 0CFFFFH 0B0000H to 0BFFFFH 0A0000H to 0AFFFFH 090000H to 09FFFFH 080000H to 08FFFFH 070000H to 07FFFFH 060000H to 06FFFFH 050000H to 05FFFFH 040000H to 04FFFFH 030000H to 03FFFFH 020000H to 02FFFFH 010000H to 01FFFFH 00E000H to 00FFFFH 00C000H to 00DFFFH 00A000H to 00BFFFH 008000H to 009FFFH 006000H to 007FFFH 004000H to 005FFFH 002000H to 003FFFH 000000H to 001FFFH (x16) Address range 0D8000H to 0DFFFFH 0D0000H to 0D7FFFH 0C8000H to 0CFFFFH 0C0000H to 0C7FFFH 0B8000H to 0BFFFFH 0B0000H to 0B7FFFH 0A8000H to 0AFFFFH 0A0000H to 0A7FFFH 098000H to 09FFFFH 090000H to 097FFFH 088000H to 08FFFFH 080000H to 087FFFH 078000H to 07FFFFH 070000H to 077FFFH 068000H to 06FFFFH 060000H to 067FFFH 058000H to 05FFFFH 050000H to 057FFFH 048000H to 04FFFFH 040000H to 047FFFH 038000H to 03FFFFH 030000H to 037FFFH 028000H to 02FFFFH 020000H to 027FFFH 018000H to 01FFFFH 010000H to 017FFFH 008000H to 00FFFFH 007000H to 007FFFH 006000H to 006FFFH 005000H to 005FFFH 004000H to 004FFFH 003000H to 003FFFH 002000H to 002FFFH 001000H to 001FFFH 000000H to 000FFFH
MBM29DL323BD Bottom Boot Sector Architecture
Note: The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH).
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MBM29DL32XTD/BD-80/90/12
Table 8.1 Sector Address Tables (MBM29DL324TD) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 Bank 2 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 Bank 1 SA33 SA34 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address range 000000H to 00FFFFH 010000H to 01FFFFH 020000H to 02FFFFH 030000H to 03FFFFH 040000H to 04FFFFH 050000H to 05FFFFH 060000H to 06FFFFH 070000H to 07FFFFH 080000H to 08FFFFH 090000H to 09FFFFH 0A0000H to 0AFFFFH 0B0000H to 0BFFFFH 0C0000H to 0CFFFFH 0D0000H to 0DFFFFH 0E0000H to 0EFFFFH 0F0000H to 0FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1FFFFFH 200000H to 20FFFFH 210000H to 21FFFFH 220000H to 22FFFFH (x16) Address range 000000H to 007FFFH 008000H to 00FFFFH 010000H to 017FFFH 018000H to 01FFFFH 020000H to 027FFFH 028000H to 02FFFFH 030000H to 037FFFH 038000H to 03FFFFH 040000H to 047FFFH 048000H to 04FFFFH 050000H to 057FFFH 058000H to 05FFFFH 060000H to 067FFFH 068000H to 06FFFFH 070000H to 077FFFH 078000H to 07FFFFH 080000H to 087FFFH 088000H to 08FFFFH 090000H to 097FFFH 098000H to 09FFFFH 0A0000H to 0A7FFFH 0A8000H to 0AFFFFH 0B0000H to 0B7FFFH 0B8000H to 0BFFFFH 0C0000H to 0C7FFFH 0C8000H to 0CFFFFH 0D0000H to 0D7FFFH 0D8000H to 0DFFFFH 0E0000H to 0E7FFFH 0E8000H to 0EFFFFH 0F0000H to 0F7FFFH 0F8000H to 0FFFFFH 100000H to 107FFFH 108000H to 10FFFFH 110000H to 117FFFH
(Continued)
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MBM29DL32XTD/BD-80/90/12
(Continued)
Bank Sector SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 Bank 1 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 (x8) Address range 230000H to 23FFFFH 240000H to 24FFFFH 250000H to 25FFFFH 260000H to 26FFFFH 270000H to 27FFFFH 280000H to 28FFFFH 290000H to 29FFFFH 2A0000H to 2AFFFFH 2B0000H to 2BFFFFH 2C0000H to 2CFFFFH 2D0000H to 2DFFFFH 2E0000H to 2EFFFFH 2F0000H to 2FFFFFH 300000H to 30FFFFH 310000H to 31FFFFH 320000H to 32FFFFH 330000H to 33FFFFH 340000H to 34FFFFH 350000H to 35FFFFH 360000H to 36FFFFH 370000H to 37FFFFH 380000H to 38FFFFH 390000H to 39FFFFH 3A0000H to 3AFFFFH 3B0000H to 3BFFFFH 3C0000H to 3CFFFFH 3D0000H to 3DFFFFH 3E0000H to 3EFFFFH 3F0000H to 3F1FFFH 3F2000H to 3F3FFFH 3F4000H to 3F5FFFH 3F6000H to 3F7FFFH 3F8000H to 3F9FFFH 3FA000H to 3FBFFFH 3FC000H to 3FDFFFH 3FE000H to 3FFFFFH (x16) Address range 118000H to 11FFFFH 120000H to 127FFFH 128000H to 12FFFFH 130000H to 137FFFH 138000H to 13FFFFH 140000H to 147FFFH 148000H to 14FFFFH 150000H to 157FFFH 158000H to 15FFFFH 160000H to 167FFFH 168000H to 16FFFFH 170000H to 177FFFH 178000H to 17FFFFH 180000H to 187FFFH 188000H to 18FFFFH 190000H to 197FFFH 198000H to 19FFFFH 1A0000H to 1A7FFFH 1A8000H to 1AFFFFH 1B0000H to 1B7FFFH 1B8000H to 1BFFFFH 1C0000H to 1C7FFFH 1C8000H to 1CFFFFH 1D0000H to 1D7FFFH 1D8000H to 1DFFFFH 1E0000H to 1E7FFFH 1E8000H to 1EFFFFH 1F0000H to 1F7FFFH 1F8000H to 1F8FFFH 1F9000H to 1F9FFFH 1FA000H to 1FAFFFH 1FB000H to 1FBFFFH 1FC000H to 1FCFFFH 1FD000H to 1FDFFFH 1FE000H to 1FEFFFH 1FF000H to 1FFFFFH
MBM29DL324TD Top Boot Sector Architecture
Note: The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH).
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MBM29DL32XTD/BD-80/90/12
Table 8.2 Sector Address Tables (MBM29DL324BD) Bank Sector SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 Bank 2 SA54 SA53 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 SA38 SA37 Bank 1 SA36 SA35 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address range 3F0000H to 3FFFFFH 3E0000H to 3EFFFFH 3D0000H to 3DFFFFH 3C0000H to 3CFFFFH 3B0000H to 3BFFFFH 3A0000H to 3AFFFFH 390000H to 39FFFFH 380000H to 38FFFFH 370000H to 37FFFFH 360000H to 36FFFFH 350000H to 35FFFFH 340000H to 34FFFFH 330000H to 33FFFFH 320000H to 32FFFFH 310000H to 31FFFFH 300000H to 30FFFFH 2F0000H to 2FFFFFH 2E0000H to 2EFFFFH 2D0000H to 2DFFFFH 2C0000H to 2CFFFFH 2B0000H to 2BFFFFH 2A0000H to 2AFFFFH 290000H to 29FFFFH 280000H to 28FFFFH 270000H to 27FFFFH 260000H to 26FFFFH 250000H to 25FFFFH 240000H to 24FFFFH 230000H to 23FFFFH 220000H to 22FFFFH 210000H to 21FFFFH 200000H to 20FFFFH 1F0000H to 1FFFFFH 1E0000H to 1EFFFFH 1D0000H to 1DFFFFH 1C0000H to 1CFFFFH (x16) Address range 1F8000H to 1FFFFFH 1F0000H to 1F7FFFH 1E8000H to 1EFFFFH 1E0000H to 1E7FFFH 1D8000H to 1DFFFFH 1D0000H to 1D7FFFH 1C8000H to 1CFFFFH 1C0000H to 1C7FFFH 1B8000H to 1BFFFFH 1B0000H to 1B7FFFH 1A8000H to 1AFFFFH 1A0000H to 1A7FFFH 198000H to 19FFFFH 190000H to 197FFFH 188000H to 18FFFFH 180000H to 187FFFH 178000H to 17FFFFH 170000H to 177FFFH 168000H to 16FFFFH 160000H to 167FFFH 158000H to 15FFFFH 150000H to 157FFFH 148000H to 14FFFFH 140000H to 147FFFH 138000H to 13FFFFH 130000H to 137FFFH 128000H to 12FFFFH 120000H to 127FFFH 118000H to 11FFFFH 110000H to 117FFFH 108000H to 10FFFFH 100000H to 107FFFH 0F8000H to 0FFFFFH 0F0000H to 0F7FFFH 0E8000H to 0EFFFFH 0E0000H to 0E7FFFH
(Continued)
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MBM29DL32XTD/BD-80/90/12
(Continued)
Bank Sector SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 Bank 1 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Sector address Sector size Bank address (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 0 0 1 1 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 (x8) Address range 1B0000H to 1BFFFFH 1A0000H to 1AFFFFH 190000H to 19FFFFH 180000H to 18FFFFH 170000H to 17FFFFH 160000H to 16FFFFH 150000H to 15FFFFH 140000H to 14FFFFH 130000H to 13FFFFH 120000H to 12FFFFH 110000H to 11FFFFH 100000H to 10FFFFH 0F0000H to 0FFFFFH 0E0000H to 0EFFFFH 0D0000H to 0DFFFFH 0C0000H to 0CFFFFH 0B0000H to 0BFFFFH 0A0000H to 0AFFFFH 090000H to 09FFFFH 080000H to 08FFFFH 070000H to 07FFFFH 060000H to 06FFFFH 050000H to 05FFFFH 040000H to 04FFFFH 030000H to 03FFFFH 020000H to 02FFFFH 010000H to 01FFFFH 00E000H to 00FFFFH 00C000H to 00DFFFH 00A000H to 00BFFFH 008000H to 009FFFH 006000H to 007FFFH 004000H to 005FFFH 002000H to 003FFFH 000000H to 001FFFH (x16) Address range 0D8000H to 0DFFFFH 0D0000H to 0D7FFFH 0C8000H to 0CFFFFH 0C0000H to 0C7FFFH 0B8000H to 0BFFFFH 0B0000H to 0B7FFFH 0A8000H to 0AFFFFH 0A0000H to 0A7FFFH 098000H to 09FFFFH 090000H to 097FFFH 088000H to 08FFFFH 080000H to 087FFFH 078000H to 07FFFFH 070000H to 077FFFH 068000H to 06FFFFH 060000H to 067FFFH 058000H to 05FFFFH 050000H to 057FFFH 048000H to 04FFFFH 040000H to 047FFFH 038000H to 03FFFFH 030000H to 037FFFH 028000H to 02FFFFH 020000H to 027FFFH 018000H to 01FFFFH 010000H to 017FFFH 008000H to 00FFFFH 007000H to 007FFFH 006000H to 006FFFH 005000H to 005FFFH 004000H to 004FFFH 003000H to 003FFFH 002000H to 002FFFH 001000H to 001FFFH 000000H to 000FFFH
MBM29DL324BD Bottom Boot Sector Architecture
Note: The address range is A20: A-1 if in byte mode (BYTE = VIL). The address range is A20: A0 if in word mode (BYTE = VIH).
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MBM29DL32XTD/BD-80/90/12
Table 9.1 Sector Group Addresses (MBM29DL32XTD) (Top Boot Block) Sector group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 A20 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 A17 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 A16 0 0 1 1 X X X X X X X X X X X X X X 0 0 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 X X X SA60 to SA62 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA4 to SA7 SA8 to SA11 SA12 to SA15 SA16 to SA19 SA20 to SA23 SA24 to SA27 SA28 to SA31 SA32 to SA35 SA36 to SA39 SA40 to SA43 SA44 to SA47 SA48 to SA51 SA52 to SA55 SA56 to SA59 X X X SA1 to SA3 A14 X A13 X A12 X Sectors SA0
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MBM29DL32XTD/BD-80/90/12
Table 9.2 Sector Group Addresses (MBM29DL32XBD) (Bottom Boot Block) Sector group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 A17 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 A16 0 0 0 0 0 0 0 0 0 1 1 X X X X X X X X X X X X X X 0 0 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 X X X SA70 X X X SA67 to SA69 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 X X X SA8 to SA10 A14 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1 A12 0 1 0 1 0 1 0 1 Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7
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MBM29DL32XTD/BD-80/90/12
s FUNCTIONAL DESCRIPTION
* Simultaneous Operation
MBM29DL32XTD/BD have feature, which is capability of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank selection can be selected by bank address (A15 to A20) with zero latency. The MBM29DL321TD/BD have two banks which contain Bank 1 (8KB x eight sectors) and Bank 2 (64KB x sixty-three sectors). The MBM29DL322TD/BD have two banks which contain Bank 1 (8KB x eight sectors, 64KB x seven sectors) and Bank 2 (64KB x fifty-six sectors). The MBM29DL323TD/BD have two banks which contain Bank 1 (8KB x eight sectors, 64KB x fifteen sectors) and Bank 2 (64KB x forty-eight sectors). The MBM29DL324TD/BD have two banks which contain Bank 1 (8KB x eight sectors, 64KB x thirty-one sectors) and Bank 2 (64KB x thirty-two sectors). The simultaneous operation can not execute multi-function mode in the same bank. Table 10 shows combination to be possible for simultaneous operation. (Refer to the Figure 11 Back-to-back Read/Write Timing Diagram.) Table 10 Simultaneous Operation Case 1 2 3 4 5 6 7 Bank 1 status Read Mode Read Mode Read Mode Read Mode Autoselect Mode Program Mode Erase Mode * Bank 2 status Read Mode Autoselect Mode Program Mode Erase Mode * Read Mode Read Mode Read Mode
*: An erase operation may also be supended to read from or program to a sector not being erased.
* Read Mode
The MBM29DL32XTD/BD have two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from "H" or "L"
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MBM29DL32XTD/BD-80/90/12
* Standby Mode
There are two ways to implement the standby mode on the MBM29DL32XTD/BD devices, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC 0.3 V. Under this condition the current consumed is less than 5 A max. During Embedded Algorithm operation, VCC active current (ICC2) is required even CE = "H". The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS 0.3 V (CE = "H" or "L"). Under this condition the current is consumed is less than 5 A max. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs are valid for read access. In the standby mode the outputs are in the high impedance state, independent of the OE input.
* Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29DL32XTD/BD data. This mode can be used effectively with an application requested low power consumption such as handy terminals. To activate this mode, MBM29DL32XTD/BD automatically switch themselves to low power mode when MBM29DL32XTD/BD addresses remain stably during access fine of 150 ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 A (CMOS Level). During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically and MBM29DL32XTD/BD read-out the data for changed addresses.
* Output Disable
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state.
* Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the devices. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON'T CARES except A0, A1, and A6 (A-1). (See Tables 3 and 4.) The manufacturer and device codes may also be read via the command register, for instances when the MBM29DL32XTD/BD are erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 12. (Refer to Autoselect Command section.)
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Byte 0 (A0 = VIL) represents the manufacturer's code (Fujitsu = 04H) and word 1 (A0 = VIH) represents the device identifier code (MBM29DL321TD = 59H and MBM29DL321BD = 5AH for x8 mode; MBM29DL321TD = 2259H and MBM29DL321BD = 225AH for x16 mode). (MBM29DL322TD = 55H and MBM29DL322BD = 56H for x8 mode; MBM29DL322TD = 2255H and MBM29DL322BD = 2256H for x16 mode). (MBM29DL323TD = 50H and MBM29DL323BD = 53H for x8 mode; MBM29DL323TD = 2250H and MBM29DL323BD = 2253H for x16 mode). (MBM29DL324TD = 5CH and MBM29DL324BD = 5FH for x8 mode; MBM29DL324TD = 225CH and MBM29DL324BD = 225FH for x16 mode). These two bytes/words are given in the tables 11.1 to 11.8. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See Tables 11.1 to 11.8.) In case of applying VID on A9, since both Bank 1 and Bank 2 enters Autoselect mode, the simultenous operation can not be executed. Table 11.1 MBM29DL321TD/BD Sector Group Protection Verify Autoselect Codes Type Manufacture's Code Byte MBM29DL321TD Device Code MBM29DL321BD Word Sector Group Protection *1: A-1 is for Byte mode. *2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses. Table 11.2 Expanded Autoselect Code Table Type Manufacturer's Code (B) MBM29DL321TD Device Code MBM29DL321BD (W) 225AH 0 Sector Group Protection (B): Byte mode (W): Word mode 01H
A-1/0
A12 to A20 X X Word Byte X Sector Group Addresses
A6 VIL VIL
A1 VIL VIL
A0 VIL VIH
A-1*1 VIL VIL X VIL
Code (HEX) 04H 59H 2259H 5AH 225AH 01H*2
VIL
VIL
VIH X
VIL
VIH
VIL
VIL
Code 04H
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A-1/0
0
0
0
0
0
0
0
0
0 1 1 1 1 0
0 0 0 0 0 0
0 1 1 1 1 0
0 1 1 1 1 0
1 0 0 0 0 0
0 0 0 1 1 0
0 1 1 0 0 1
59H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 0 0 0 1 0 0
(W) 2259H 0 (B)
5AH A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
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Table 11.3 MBM29DL322TD/BD Sector Group Protection Verify Autoselect Codes Type Manufacture's Code Byte MBM29DL322TD Device Code MBM29DL322BD Word Sector Group Protection *1: A-1 is for Byte mode. *2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses. Table 11.4 Expanded Autoselect Code Table Type Manufacturer's Code (B) MBM29DL322TD Device Code MBM29DL322BD (W) 2256H 0 Sector Group Protection (B): Byte mode (W): Word mode 01H
A-1/0
A12 to A20 X X Word Byte X Sector group addresses
A6 VIL VIL
A1 VIL VIL
A0 VIL VIH
A-1*1 VIL VIL X VIL
Code (HEX) 04H 55H 2255H 56H 2256H 01H*2
VIL
VIL
VIH X
VIL
VIH
VIL
VIL
Code 04H
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A-1/0
0
0
0
0
0
0
0
0
0 1 1 1 1 0
0 0 0 0 0 0
0 1 1 1 1 0
0 0 0 0 0 0
1 1 1 1 1 0
0 0 0 1 1 0
0 1 1 0 0 1
55H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 0 0 0 1 0 0
(W) 2255H 0 (B)
56H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
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Table 11.5 MBM29DL323TD/BD Sector Group Protection Verify Autoselect Codes Type Manufacture's Code Byte MBM29DL323TD Device Code MBM29DL323BD Word Sector Group Protection *1: A-1 is for Byte mode. *2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses. Table 11.6 Expanded Autoselect Code Table Type Manufacturer's Code (B) MBM29DL323TD Device Code MBM29DL323BD (W) 2253H 0 Sector Group Protection (B): Byte mode (W): Word mode 01H
A-1/0
A12 to A20 X X Word Byte X Sector group addresses
A6 VIL VIL
A1 VIL VIL
A0 VIL VIH
A-1*1 VIL VIL X VIL
Code (HEX) 04H 50H 2250H 53H 2253H 01H*2
VIL
VIL
VIH X
VIL
VIH
VIL
VIL
Code 04H
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A-1/0
0
0
0
0
0
0
0
0
0 1 1 1 1 0
0 0 0 0 0 0
0 1 1 1 1 0
0 0 0 0 0 0
1 0 0 0 0 0
0 0 0 1 1 0
0 0 0 1 1 1
50H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 0 0 0 1 0 0
(W) 2250H 0 (B)
53H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
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Table 11.7 MBM29DL324TD/BD Sector Group Protection Verify Autoselect Codes Type Manufacture's Code Byte MBM29DL324TD Device Code MBM29DL324BD Word Sector Group Protection *1: A-1 is for Byte mode. *2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses. Table 11.8 Expanded Autoselect Code Table Type Manufacturer's Code (B) MBM29DL324TD Device Code MBM29DL324BD (W) 225FH 0 Sector Group Protection (B): Byte mode (W): Word mode 01H
A-1/0
A12 to A20 X X Word Byte X Sector group addresses
A6 VIL VIL
A1 VIL VIL
A0 VIL VIH
A-1*1 VIL VIL X VIL
Code (HEX) 04H 5CH 225CH 5FH 225FH 01H*2
VIL
VIL
VIH X
VIL
VIH
VIL
VIL
Code 04H
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A-1/0
0
0
0
0
0
0
0
0
0 1 1 1 1 0
0 0 0 0 0 0
0 1 1 1 1 0
0 1 1 1 1 0
1 1 1 1 1 0
0 0 0 1 1 0
0 0 0 1 1 1
5CH A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 0 0 0 1 0 0
(W) 225CH 0 (B)
5FH A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
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MBM29DL32XTD/BD-80/90/12
* Write
Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
* Sector Group Protection
The MBM29DL32XTD/BD feature hardware sector group protection. This feature will disable both program and erase operations in any combination of twenty five sector groups of memory. (See Tables 9.1 and 9.2). The sector group protection feature is enabled using programming equipment at the user's site. The device is shipped with all sector groups unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V), CE = VIL and A0 = A6 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. Tables 5.1 to 8.2 define the sector address for each of the seventy one (71) individual sectors, and tables 9.1 and 9.2 define the sector group address for each of the twenty five (25) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See Figures 18 and 26 for sector group protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" code at device output DQ0 for a protected sector. Otherwise the device will produce "0" for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON'T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to VIL on byte mode. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02H, where the higher order addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical "1" at DQ0 for a protected sector group. See Tables 11.1 to 11.8 for Autoselect codes.
* Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the MBM29DL32XTD/BD devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to Figures 19 and 27.
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* RESET Hardware Reset
The MBM29DL32XTD/BD devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least "tRP" in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode "tREADY" after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an additional "tRH" before it will allow read access. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 14 for the timing diagram. Refer to Temporary Sector Group Unprotection for additional functionality.
* Boot Block Sector Protection
The Write Protection function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two "outermost" 8K byte boot sectors independently of whether those sectors were protected or unprotected using the method described in "Sector Protection/Unprotection". The two outermost 8K byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-congfigured device. (MBM29DL32XTD: SA69 and SA70, MBM29DL32XBD: SA0 and SA1) If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8K byte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in "Sector protection/unprotection".
* Accelerated Program Operation
MBM29DL32XTD/BD offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. This function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. The system would use a fact program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/ ACC pin while programming. See Figure 21.
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Table 12 MBM29DL32XTD/BD Command Definitions Command sequence
Read/Reset Read/Reset Bus write cycles req'd
Fourth bus Fifth bus Sixth bus read/write write cycle write cycle cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data First bus Second bus Third bus write cycle write cycle write cycle XXXH F0H -- -- -- -- F0H -- RA -- RD -- -- -- -- -- -- -- --
Word Byte Word Byte Word
1 3
Autoselect
3
Byte Word Byte
Program
4 1 1 6 6 1 1 3 2 2 4 1 3 4 6
Program Suspend Program Resume Chip Erase
Word Byte Word Byte
Sector Erase
Erase Suspend Erase Resume
Set to Fast Mode Fast Program *1 Reset from Fast Mode *1 Extended Sector Group Protection *2 Query *3 Hi-ROM Entry Hi-ROM Program *4 Hi-ROM Erase *4
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word
555H 2AAH 555H AAH 55H AAAH 555H AAAH (BA) 555H 2AAH 555H AAH 55H (BA) AAAH 555H AAAH 555H 2AAH 555H AAH 55H AAAH 555H AAAH BA B0H -- -- -- BA 30H -- -- -- 555H 2AAH 555H AAH 55H AAAH 555H AAAH 555H 2AAH 555H AAH 55H AAAH 555H AAAH BA B0H -- -- -- BA 30H -- -- -- 555H 2AAH 555H AAH 55H AAAH 555H AAAH XXXH A0H PA PD -- XXXH BA XXXH 90H F0H -- BA XXXH XXXH 60H 55H AAH 555H AAAH 555H AAAH 555H AAAH 555H 98H AAH SPA -- 60H -- SPA --
90H
--
--
--
--
--
--
A0H -- --
PA
PD
--
--
--
--
-- -- -- -- -- -- -- -- -- -- -- -- 555H 2AAH 555H 80H AAH 55H 10H AAAH 555H AAAH 555H 2AAH 80H AAH 55H SA 30H AAAH 555H -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20H -- -- 40H -- -- -- -- SPA -- -- -- -- SD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- HRA -- -- -- -- -- -- -- 30H
2AAH 555H 55H 88H -- -- -- -- 555H AAAH 2AAH 555H AAH 55H A0H PA PD -- -- 555H AAAH 2AAH 555H 555H 2AAH AAH 55H 80H AAH 55H 555H AAAH AAAH 555H 2AAH AAH 55H 555H
(HRBA)
Hi-ROM Exit *4
4
Byte
555H
(HRBA)
90H XXXH 00H
--
--
--
--
AAAH
AAAH
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Notes: 1. Address bits A11 to A20 = X = "H" or "L" for all address commands except or Program Address (PA), Sector Address (SA), and Bank Address (BA). 2. Bus operations are defined in Tables 3 and 4. 3. RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A15 to A20) 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse. 5. SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). SD = Sector group protection verify data. Output 01H at protected sector group addresses and output 00H at unprotected sector group addresses. 6. HRA = Address of the Hi-ROM area 29DL32XTD (Top Boot Type) Word Mode: 1F8000H to 1FFFFFH Byte Mode: 3F0000H to 3FFFFFH 29DL32XBD (Bottom Boot Type) Word Mode: 000000H to 007FFFH Byte Mode: 000000H to 00FFFFH 7. HRBA =Bank Address of the Hi-ROM area 29DL32XTD (Top Boot Type) :A15 = A16= A17 = A18 = A19 = A20 = 1 29DL32XBD (Bottom Boot Type) :A15 = A16= A17 = A18 = A19 = A20 = 0 8. The system should generate the following address patterns: Word Mode: 555H or 2AAH to addresses A0 to A10 Byte Mode: AAAH or 555H to addresses A-1 and A0 to A10 9. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*1:This command is valid while Fast Mode. *2:This command is valid while RESET = VID. *3:The valid addresses are A6 to A0. *4:This command is valid while Hi-ROM mode.
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s COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the read mode. Some commands are required Bank Address (BA) input. When command sequences are inputed to bank being read, the commands have priority than reading. Table 12 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Also the Program Suspend (B0H) and Program Resume (30H) commands are valid only while the Program operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.
* Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the command register contents are altered. The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
* Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device codes can be read from the bank, and an actual data of memory cell can be read from the another bank. Following the command write, a read cycle from address (BA)00H retrieves the manufacture code of 04H. A read cycle from address (BA)01H for x16((BA)02H for x8) returns the device code (MBM29DL321TD = 59H and MBM29DL321BD = 5AH for x8 mode; MBM29DL321TD = 2259H and MBM29DL321BD = 225AH for x16 mode). (MBM29DL322TD = 55H and MBM29DL322BD = 56H for x8 mode; MBM29DL322TD = 2255H and MBM29DL322BD = 2256H for x16 mode). (MBM29DL323TD = 50H and MBM29DL323BD = 53H for x8 mode; MBM29DL323TD = 2250H and MBM29DL323BD = 2253H for x16 mode). (MBM29DL324TD = 5CH and MBM29DL324BD = 5FH for x8 mode; MBM29DL324TD = 225CH and MBM29DL324BD = 225FH for x16 mode). (See Tables 11.1 to 11.8.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address (BA)02H for x16 ((BA)04H for x8). Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" at device output DQ0 for a protected sector group. The programming verification should be performed by verify sector group protection on the protected sector. (See Tables 8 and 9.)
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The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command sequence into the register and then Autoselect command should be written into the bank to be read. If the software (program code) for Autoselect command is stored into the Flash memory, the device and manufacture codes should be read from the other bank where is not contain the software. To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and also to write the Autoselect command during the operation, execute it after writing Read/Reset command sequence.
* Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 13, Hardware Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still "0". Only erase operations can convert "0"s to "1"s. Figure 22 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.
* Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on DQ7 is "1" (See Write Operation Status section.) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time x All sectors + Chip Program Time (Preprogramming) Figure 23 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 61
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MBM29DL32XTD/BD-80/90/12
* Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever happens later, while the command (Data = 30H) is latched on the rising edge of CE or WE which happens first. After time-out of "tTOW" from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 12. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of "tTOW" from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the "tTOW" time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 38). Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The sector erase begins after the "tTOW" time out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and terminates when the data on DQ7 is "1" (See Write Operation Status section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] x Number of Sector Erase In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe. Figure 23 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
* Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command (B0H) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30H) resumes the erase operation. The bank addresses of sector being erasing or suspending should be set when writting the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of "tSPD" to suspend the erase operation. When the devices have entered the erase-suspended mode, the 62
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RY/BY output pin will be at Hi-Z and the DQ7 bit will be at logic "1", and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address within bank being erase-suspended. To resume the operation of Sector Erase, the Resume command (30H) should be written to the bank being erase suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
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* Extended Command
(1) Fast Mode MBM29DL32XTD/BD has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. The first cycle must contain the bank address. (Refer to the Figure 28.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to the Figure 28.) (3) Extended Sector Group Protection In addition to normal sector group protection, the MBM29DL32XTD/BD has Extended Sector Group Protection as extended function. This function enable to protect sector group by forcing VID on RESET pin and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60H) into the command register. Then, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other addresses pins), and write extended sector group protection command (60H). A sector group is typically protected in 250 s. To verify programming of the protection circuitry, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40H). Following the command write, a logical "1" at device output DQ0 will produce for protected sector in the read operation. If the output data is logical "0", please repeat to write extended sector group protection command (60H) again. To terminate the operation, it is necessary to set RESET pin to VIH. (Refer to the Figures 20 and 29.) (4) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backwardcompatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98H) into the command register. The bank address should be set when writing this command. Then the device information can be read from the bank, and an actual data of memory cell be read from the another bank. Following the command write, a read cycle from specific address retrives device information. Please note that output data of upper byte (DQ8 to DQ15) is "0" in word mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary to write the read/reset command sequence into the register. (See Table 15.)
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* Hidden ROM (Hi-ROM) Region
The Hi-ROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the Hi-ROM region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The Hi-ROM region is 64K bytes in length and is stored at the same address of the 8KB x8 sectors. The MBM29DL32XTD occupies the address of the byte mode 3F0000H to 3FFFFFH (word mode 1F8000H to 1FFFFFH) and the MBM29DL32XBD type occupies the address of the byte mode 000000H to 00FFFFH (word mode 000000H to 007FFFH). After the system has written the Enter Hi-ROM command sequence, the system may read the Hi-ROM region by using the addresses normally occupied by the boot sectors. That is, the device sends all commands that would normally be sent to the boot sectors to the Hi-ROM region. This mode of operation continues until the system issues the Exit Hi-ROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors.
* Hidden ROM (Hi-ROM) Entry Command
MBM29DL32XTD/BD has a Hidden ROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program/erase is possible in this area until it is protected. However, once it is protected, it is impossible to unprotect, so please use this with caution. Hidden ROM area is 64K Byte and in the same address area of 8KB sector. The address of top boot is 3F0000H to 3FFFFFH at byte mode (1F8000H to 1FFFFFH at word mode) and the bottom boot is 000000H to 00FFFFH at byte mode (000000H to 007FFFH at word mode). These areas are normally the boot block area (8KB x8 sector). Therefore, write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called as Hidden ROM mode when the Hidden ROM area appears. Sector other than the boot block area could be read during Hidden ROM mode. Read/program/earse of the Hidden ROM area is possible during Hidden ROM mode. Write the Hidden ROM reset command sequence to exit the Hidden ROM mode. The bank address of the Hidden ROM should be set on the third cycle of this reset command sequence. In case of MBM29DL321TD/BD, whose Bank 1 size is 0.5 Mbit, the simultaneous operation cannot execute multi-function mode between the Hidden ROM area and Bank 2 Region.
* Hidden ROM (Hi-ROM) Program Command
To program the data to the Hidden ROM area, write the Hidden ROM program command sequence during Hidden ROM mode. This command is same as the program command in the past except to write the command during Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the address to be programmed. If the address other than the Hidden ROM area is selected to program, the data of the address will be changed.
* Hidden ROM (Hi-ROM) Erase Command
To erase the Hidden ROM area, write the Hidden ROM erase command sequence during Hidden ROM mode. This command is same as the sector erase command in the past except to write the command during Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the sector address to be erased. If the sector address other than the Hidden ROM area is selected, the data of the sector will be changed.
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* Hidden ROM (Hi-ROM) Protect Command
There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup command(60H), set the sector address in the Hidden ROM area and (A6, A1, A0) = (0,1,0), and write the sector group protect command(60H) during the Hidden ROM mode. The same command sequence could be used because except that it is in the Hidden ROM mode and that it does not apply high voltage to RESET pin, it is the same as the extension sector group protect in the past. Please refer to "Function Explanation Extended Command (3) Extentended Sector Group Protection" for details of extention sector group protect setting. The other is to apply high voltage (VID) to A9 and OE, set the sector address in the Hidden ROM area and (A6, A1, A0) = (0,1,0), and apply the write pulse during the Hidden ROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A1, A0) = (0,1,0) and the sector address in the Hidden ROM area, and read. When "1" appears to DQ0, the protect setting is completed. "0" will appear to DQ0 if it is not protected. Please apply write pulse agian. The same command sequence could be used for the above method because other than the Hidden ROM mode, it is the same as the sector group protect in the past. Please refer to "Function Explanation Secor Group Protection" for details of sector group protect setting Other sector group will be effected if the address other than the Hidden ROM area is selected for the sectoer group address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay closest attention.
* Write Operation Status
Detailed in Table 13 are all the status flags that can determine the status of the bank for the current mode operation. The read operation from the bank where is not operate Embedded Algorithm returns a data of memory cell. These bits offer a method for determining whether a Embedded Algorithm is completed properly. The information on DQ2 is address sensitive. This means that if an address from an erasing sector is consectively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consectively read. This allows the user to determine which sectors are erasing and which are not. The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] , [2] , [3] , the DQ6 is toggling in the case of [1] and [3]. In case of [2], the data of memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled in the [1] and [3]. In the erase suspend read mode, DQ2 is toggled in the [1] and [3]. In case of [2], the data of memory cell is outputted.
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Table 13 Hardware Sequence Flags Status Embedded Program Algorithm Embedded Erase Algorithm Program Suspend Read Program (Program Suspended Sector) Suspended Program Suspend Read Mode (Non-Program Suspended Sector) Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode DQ7 DQ7 0 Data Data 1 Data DQ7 DQ7 0 DQ7 DQ6 Toggle Toggle Data Data 1 Data Toggle Toggle Toggle Toggle DQ5 0 0 DQ3 0 1 DQ2 1 Toggle* Data Data Toggle Data 1* 1 N/A N/A
Data Data Data Data 0 0
In Progress
Data Data 0 1 1 1 0 0 1 0
*: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase suspend sector address will indicate logic "1" at the DQ2 bit. Note: 1.DQ0 and DQ1 are reserve pins for future use. 2.DQ4 is Fujitsu internal use only.
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* DQ7 Data Polling
The MBM29DL32XTD/BD devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 24. For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 s, then the bank returns to read mode. Once the Embedded Algorithm operation is close to being completed, the MBM29DL32XTD/BD data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant of time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See Table 13.) See Figure 9 for the Data Polling timing specifications and diagrams.
* DQ6 Toggle Bit I
The MBM29DL32XTD/BD also feature the "Toggle Bit I" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 s and then stop toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause the DQ6 to toggle. 68
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The system can use DQ6 to determine whether a sector is actively erasing or is erase-suspended. When a bank is actively erasing (that is, the Embedded Erase Algorithm is in progress), DQ6 toggles. When a bank enters the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during the erase-suspend-program cause DQ6 to toggle. To operate toggle bit function properly, CE or OE must be high when bank address is changed. See Figure 10 for the Toggle Bit I timing specifications and diagrams.
* DQ5 Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the devices under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in Tables 3 and 4. The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the DQ5 bit will indicate a "1." Please note that this is not a device failure condition since the devices were incorrectly used. If this occurs, reset the device with command sequence.
* DQ3 Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See Table 13: Hardware Sequence Flags.
* DQ2 Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic "1" at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows: 69
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For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also Table 14 and Figure 12. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. To operate toggle bit function properly, CE or OE must be high when bank address is changed. Table 14 Toggle Bit Status Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) Erase-Suspend Program DQ7 DQ7 0 1 DQ7 DQ6 Toggle Toggle 1 Toggle DQ2 1 Toggle (Note) Toggle 1 (Note)
Note: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from nonerase suspend sector address will indicate logic "1" at the DQ2 bit.
* RY/BY Ready/Busy
The MBM29DL32XTD/BD provide a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/ write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase commands. If the MBM29DL32XTD/BD are placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to Figures 13 and 14 for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
* Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL32XTD/BD devices. When this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0 to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer to Figures 15, 16 and 17 for the timing diagram.
* Data Protection
The MBM29DL32XTD/BD are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the devices automatically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. 70
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* Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (min). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (min). If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
* Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
* Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one.
* Power-Up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up.
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Table 15 Common Flash Memory Interface Code Description Query-unique ASCII string "QRY" Primary OEM Command Set 2h: AMD/FJ standard type Address for Primary Extended Table Alternate OEM Command Set (00h = not applicable) Address for Alternate OEM Extended Table VCC Min. (write/erase) D7-4: volt, D3-0: 100 mvolt VCC Max. (write/erase) D7-4: volt, D3-0: 100 mvolt VPP Min. voltage VPP Max. voltage Typical timeout per single byte/word write 2N S Typical timeout for Min. size buffer write 2N S Typical timeout per individual block erase 2N mS Typical timeout for full chip erase 2N mS Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical Device Size = 2N byte Flash Device Interface description Max. number of byte in multi-byte write = 2N Number of Erase Block Regions within device Erase Block Region 1 Information A0 to A6 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h
DQ0 to DQ15
0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h 0016h 0002h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h
Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0h = Required 1h = Not Required Erase Suspend 0h = Not Supported 1h = To Read Only 2h = To Read & Write Sector Protection 0h = Not Supported X = Number of sectors in per group Sector Temporary Unprotection 00h = Not Supported 01h = Supported Sector Protection Algorithm Number of Sector for Bank 2 00h = Not Supported 3Fh = MBM29DL321TD 38h = MBM29DL322TD 30h = MBM29DL323TD 20h = MBM29DL324TD 3Fh = MBM29DL321BD 38h = MBM29DL322BD 30h = MBM29DL323BD 20h = MBM29DL324BD Burst Mode Type 00h = Not Supported Page Mode Type 00h = Not Supported ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-4: volt, D3-0: 100 mvolt ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-4: volt, D3-0: 100 mvolt Boot Type 02h = MBM29DL32XBD 03h = MBM29DL32XTD
A0 to A6 40h 41h 42h 43h 44h 45h
DQ0 to DQ15
0050h 0052h 0049h 0031h 0031h 0000h
46h
0002h
47h
0001h
48h
0001h
49h 4Ah
0004h 00XXh
4Bh 4Ch 4Dh
0000h 0000h 0085h
4Eh
0095h
4Fh
00XXh
Erase Block Region 2 Information
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s FLOW CHART
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (See below)
Data Polling Device
Increment Address
No
Last Address ? Yes
Programming Completed
Program Command Sequence* (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
* : The sequence is applied for x 16 mode. The addresses differ from x 8 mode.
Figure 22 Embedded ProgramTM Algorithm
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EMBEDDED ALGORITHMS
Start
Write Erase Command Sequence (See below) Data Polling or Toggle Bit Successfully Completed
Erasure Completed Individual Sector/Multiple Sector* Erase Command Sequence (Address/Command): 555H/AAH
Chip Erase Command Sequence* (Address/Command): 555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
Sector Address/30H
Additional sector erase commands are optional.
Sector Address/30H
* : The sequence is applied for x 16 mode. The addresses differ from x 8 mode.
Figure 23 Embedded EraseTM Algorithm
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Start
Read (DQ 0 to DQ 7) Addr. = VA
DQ 7 = Data? No No DQ 5 = 1? Yes Read (DQ 0 to DQ 7) Addr. = VA
Yes
VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = Any of the sector addresses within the sector not being protected during chip erase
DQ 7 = Data? No Fail
Yes
Pass
Note: DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 24 Data Polling Algorithm
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MBM29DL32XTD/BD-80/90/12
Start
Read (DQ 0 to DQ 7) Addr. = VA
VA = Bank address being executed Embedded Algorithm.
No
DQ 6 = Toggle ? Yes No DQ 5 = 1? Yes Read (DQ 0 to DQ 7) Addr. = VA
DQ 6 = Toggle ? Yes Fail
No
Pass
Note: DQ6 is rechecked even if DQ5 = "1" because DQ6 may stop toggling at the same time as DQ5 changing to "1" .
Figure 25 Toggle Bit Algorithm
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MBM29DL32XTD/BD-80/90/12
Start
Setup Sector Group Addr. (A20, A19, A18, A17, A16, A15, A14, A13, A12)
PLSCNT = 1
OE = V ID, A 9 = V ID, A 6 = CE = V IL, RESET = V IH A 0 = V IL, A 1 = V IH Activate WE Pulse
Increment PLSCNT
Time out 100 s
WE = V IH, CE = OE = V IL (A 9 should remain V ID)
Read from Sector Group (Addr. = SGA, A 0 = V IL, A 1 = V IH, A 6 = V IL)* No No PLSCNT = 25? Yes Remove V ID from A 9 Write Reset Command Data = 01H? Yes Yes Protect Another Sector Group ? No Remove V ID from A 9 Write Reset Command
Device Failed
Sector Group Protection Completed
* : A-1 is V IL on byte mode.
Figure 26 Sector Group Protection Algorithm
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MBM29DL32XTD/BD-80/90/12
Start
RESET = VID (Note 1)
Perform Erase or Program Operations
RESET = VIH
Temporary Sector Group Unprotection Completed (Note 2)
Notes: 1. All protected sector groups are unprotected. 2. All previously protected sector groups are protected once again.
Figure 27 Temporary Sector Group Unprotection Algorithm
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MBM29DL32XTD/BD-80/90/12
FAST MODE ALGORITHM
Start
555H/AAH
2AAH/55H
Set Fast Mode
555H/20H
XXXH/A0H
Program Address/Program Data
Data Polling Device
Verify Byte? Yes No
No
In Fast Program
Increment Address
Last Address ? Yes Programming Completed
(BA) XXXH/90H Reset Fast Mode XXXH/F0H
Note: The sequence is applied for x 16 mode. The addresses differ from x 8 mode. Figure 28 Embedded ProgramTM Algorithm for Fast Mode
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MBM29DL32XTD/BD-80/90/12
Start
RESET = VID
Wait to 4 s
Device is Operating in Temporary Sector Group Unprotection Mode
No
Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXH/60H
PLSCNT = 1
To Sector Group Protection Write SGA/60H (A0 = VIL, A1 = VIH, A6 = VIL)
Increment PLSCNT
Time Out 250 s Setup Next Sector Group Address
To Verify Sector Group Protection Write SGA/40H (A0 = VIL, A1 = VIH, A6 = VIL) Read from Sector Group Address (A0 = VIL, A1 = VIH, A6 = VIL) No No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Data = 01H? Yes
Yes Protection Other Sector Group ? No
Device Failed
Remove VID from RESET Write Reset Command
Sector Group Protection Completed
Figure 29 Extended Sector Group Protection Algorithm
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MBM29DL32XTD/BD-80/90/12
s ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29DL32X
T
D
80
PFTN
PACKAGE TYPE PFTN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout PBT = Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION
BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector
DEVICE NUMBER/DESCRIPTION MBM29DL32X 32Mega-bit (4M x 8-Bit or 2M x 16-Bit) CMOS Dual Operation Flash Memory 3.0 V-only Read, Program, and Erase
Valid Combinations MBM29DL321TD/BD MBM29DL322TD/BD MBM29DL323TD/BD MBM29DL324TD/BD 80 90 12 PFTN PFTR PBT
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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MBM29DL32XTD/BD-80/90/12
s PACKAGE DIMENSIONS
48-pin plastic TSOP(I) (FPT-48P-M19)
LEAD No.
1 48
* Resin Protrusion. (Each Side: 0.15 (.006)Max)
INDEX
Details of "A" part 0.15(.006) MAX
"A" 0.15(.006)
0.35(.014) MAX 0.25(.010)
24
25
20.000.20 (.787.008) * 18.400.20 (.724.008)
* 12.000.20
(.472.008) 11.50REF (.460) 1.10 -0.05
+0.10 +.004
.043 -.002 (Mounting height)
0.10(.004)
0.50(.0197) TYP 0.150.05 (.006.002) 0.200.10 (.008.004)
0.05(0.02)MIN (STAND OFF) 0.10(.004)
M
19.000.20 (.748.008)
0.500.10 (.020.004)
C
1996 FUJITSU LIMITED F48029S-2C-2
Dimensions in mm (inches)
48-pin plastic TSOP(I) (FPT-48P-M20)
LEAD No.
1 48
* Resin Protrusion. (Each Side: 0.15 (.006)Max)
INDEX
Details of "A" part 0.15(.006) MAX
"A" 0.15(.006)
0.35(.014) MAX 0.25(.010)
24
25
19.000.20 (.748.008)
0.500.10 (.020.004) 0.150.10 (.006.002) 0.200.10 (.008.004) 0.10(.004)
M
0.10(.004)
0.50(.0197) TYP
0.05(0.02)MIN (STAND OFF)
1.10 -0.05
+0.10 +.004
* 18.400.20
(.724.008) 20.000.20 (.787.008)
11.50(.460)REF
.043 -.002 (Mounting height)
* 12.000.20(.472.008)
C
1996 FUJITSU LIMITED F48030S-2C-2
Dimensions in mm (inches)
(Continued)
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MBM29DL32XTD/BD-80/90/12
(Continued)
57-pin plastic FBGA (BGA-57P-M01)
(8.80(.346)) (7.20(.283)) 13.950.05(.549.002) 1.05 .041
+0.15 -0.10 +.006 -.004
(Mounting height)
(5.60(.220)) 0.80(.031) TYP 8 7 6 5 4 3 2 1 ML K JHGFEDCBA
7.950.05 (.313.002) INDEX
0.80(.031) (5.60(.220)) TYP (4.00(.157))
C0.25(.010)
0.360.10 (Stand off) (.014.004)
INDEX BALL 57-O0.450.05 (57-O.018.002) 0.08(.003)
M
0.10(.004)
C
1998 FUJITSU LIMITED B57001S-1C-1
Dimensions in mm (inches)
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MBM29DL32XTD/BD-80/90/12
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9909 (c) FUJITSU LIMITED Printed in Japan

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